1. Field of the Invention
The present invention relates to a semiconductor device having an organic element. In particular, the invention relates to a semiconductor device having a memory circuit using an organic element.
2. Description of the Related Art
In accordance with the development of computer technology and improvement of image recognition technology, data recognition using a medium such as a barcode has been widely used, which is used, for example, for data recognition of merchandise. A further larger amount of data recognition is expected to be processed in the future. However, data reading or the like using a barcode is disadvantageous in that a barcode reader is required to contact the barcode and the amount of data stored in a barcode is not very large. Therefore, data recognition without contact and increase of the memory capacity of a medium have been demanded.
In response to such demand, an ID chip using an IC has been developed in recent years. An ID chip stores required data in a memory circuit within an IC chip and the data is read out by using a non-contact means, that is generally a wireless means. It is expected that commercial distribution and the like become simpler, cost thereof be reduced, and high security be provided when the ID chip comes into a practical use.
An overview of an individual recognition system using an ID chip is described with reference to FIG. 4. FIG. 4 illustrates an overview of an individual recognition system for obtaining individual data on a bag without contact. An ID chip 401 storing particular individual data is attached to or embedded in a bag 404. A radio wave is transmitted from an antenna unit 402 of an interrogator (also referred to as a reader/writer) 403 to the ID chip. When receiving the radio wave, the ID chip 401 sends back the individual data thereof to the antenna unit 402. The antenna unit 402 sends the individual data to the interrogator to discriminate it in the interrogator. In this manner, the interrogator can obtain data on the bag 404. Furthermore, this system enables physical distribution management, counting, exclusion of a counterfeit, and the like.
An example of such an ID chip technology is shown in FIG. 2. A semiconductor device 200 used as an ID chip includes an antenna circuit 201, a rectifier circuit 202, a stabilizing power source circuit 203, an amplifier 208, a demodulating circuit 213, a logic circuit 209, a memory control circuit 212, a memory circuit 211, a logic circuit 207, an amplifier 206, and a modulating circuit 205. Further, the antenna circuit 201 includes an antenna coil 301 and a tuning capacitor 302 (FIG. 3A). The rectifier circuit 202 includes diodes 303 and 304 and a smoothing capacitor 305 (FIG. 3B). The portions other than the antenna circuit 201 are called a signal processing circuit 214.
An operation of the ID chip is described below. An AC signal received by the antenna circuit 201 is half-wave rectified by the diodes 303 and 304 and then smoothed by the smoothing capacitor 305. The smoothed voltage containing a number of ripples is stabilized by the stabilizing power source circuit 203, and the stabilized voltage is supplied to the demodulating circuit 213, the amplifier 206, the logic circuit 207, the amplifier 208, the logic circuit 209, the memory circuit 211, and the memory control circuit 212. On the other hand, a signal received by the antenna circuit 201 is inputted to the logic circuit 209 as a clock signal through the amplifier 208. Further, a signal inputted from the antenna is demodulated by the demodulating circuit 213 and inputted as data to the logic circuit 209.
In the logic circuit 209, the inputted data is decoded. The interrogator sends data after having encoded it with a deformation mirror code, an NRZ-L code, or the like and it is decoded by the logic circuit 209. The decoded data is sent to the memory control circuit 212, thereby data stored in the memory circuit 211 is read out. It is necessary that the memory circuit 211 be a nonvolatile memory circuit which is capable of storing data even when the power is OFF, and a mask ROM, an EEPROM, a flash memory, or the like is employed. The stored content is, for example, 16-byte data (see FIG. 12) which includes a 4-byte family code for indicating a series of the ID chip, a 4-byte application code, and two kinds of 4-byte user codes set by a user.
As for a transmitted/received signal, 125 kHz, 13.56 MHz, 915 MHz, 2.45 GHz or the like may be employed, to which the ISO standard or the like is applied. In addition, a modulation and demodulation system in transmission/reception is standardized. An example of such an ID chip is disclosed in Patent Document 1.
In an EEPROM and a flash memory, a transistor has a structure in which gates are overlapped such as a floating gate structure. In the case of using a floating gate in a thin film transistor (hereinafter TFT), the floating gate transistor is structured by a substrate 601, a base film 602, an active layer 603, a first gate insulating film 604, a floating gate 605, a second gate insulating film 606, a control gate 607, an interlayer film 608, a source electrode 609, and a drain electrode 610 as shown in FIG. 6.
A flash memory is constituted by connecting floating gate transistors in series as shown in FIG. 5. In FIG. 5, the flash memory includes floating gate transistors 501 to 512, switches 513 to 518, current sources 519 to 521, a voltage source 522, power source terminals 523 to 527, signal lines 528 to 531, and sense amplifiers 532 to 534. In the case of writing data, a voltage is applied to the floating gate transistors through the switches 513, 515 and 517 from the voltage source 522. Further, the transistors can be selected by controlling the signal lines 528 to 531.
In the case of reading out data, a current is applied to the floating gate transistors through the switches 514, 516 and 518 from the current sources 519 to 521 respectively. A potential at this time is amplified by the sense amplifiers 532 to 534, and then taken out as a signal. Description on a flash memory is made in the following document (see Non-Patent Document 1).
Patent Document 1
Japanese Patent Laid-Open No. 2001-250393
Non-Patent Document 1
F. Masuoka, “Rapidly-Advancing Flash Memory”, pp. 91-154, published by Kogyochosakai Publishing Co., Ltd.
A conventional semiconductor device for an ID chip, described above has the following problems. In the case of using a mask ROM as a nonvolatile memory, data is written thereinto in a step of manufacturing the chip, and thus no data can be written after manufactured.
An EEPROM and a flash memory are effective as a nonvolatile memory capable of being rewritten. Since these memories store data by holding a charge in a second gate insulating film thereof, the quality of the gate insulating film is required to be high in order to keep the holding capability. However, when the transistor is formed over an insulating substrate such as glass, high-temperature treatment over 600° C. cannot be performed. Accordingly, the quality of the gate insulating film can be improved only to a limited degree, which makes it difficult to achieve a good nonvolatile memory.